wICE – Basic CPU Architecture and Optimization

wICE - Basic CPU Architecture and Optimization

Purpose and Program

This 2-day training is offered by NEC, the vendor of our new Tier-2 cluster wICE. A more advanced training is also scheduled to build up on this training, for users who would like to dive deeper into using HPC infrastructures. Here is  a brief schetch of the program.

• General system overview (CPU, memory, network, I/O, SMT, ...)
• Compilers (Intel, GNU, advanced options)
• Commonly used libraries (MKL)
• Parallelization (OpenMP, MPI, process/thread pinning)
• Vectorization
• Tuning and optimization (performance analysis, tools, techniques, reports)
• Performance scaling
• Debugging

Target Audience This training is suited for

• researches who are developing their own source code
• users which are porting a serial code to work in parallel (multi-threading of multi-processing)
• developers who are planning to port a working software (on a different platform) to run it on VSC machines
• users of parallel software who like to gain deeper insight into efficient use of compute architecture

Date

Tuesday 22 November and Wednesday 23 November, starting from 9:00 am until 17:00 pm.

Venue

Opleidingscentrum A KU Leuven Willem De Croylaan 52A BE-3001 Heverlee, Belgium

Prerequisites If you already have a VSC account, be ready to login to Tier-2 for the hands-on exercieses.

Follow up Training Immediately after this trainig, we have also scheduled an advanced training to dive deeper into the few selected topics. You are adviced to also sign up for the Advanced Training.