wICE - Advanced CPU Architecture and Optimization

wICE - Advanced CPU Architecture and Optimization

Purpose and Program

This 2-day training is offered by NEC, the vendor of our new Tier-2 cluster wICE, and follows the basic training on the same topic. Here is  a brief schetch of the program.

• Multi-threading (OpenMP programming)
• Multi-processing (MPI programming)
• Performance analysis (Roofline model, ITAC)
• Tuning and optimization (cache blocking)
• Debugging tools (GDB, Valgrind)

Target Audience This training is tailord to users

• who are familiar with the basics of HPC architecture, parallelism and optimization, but would like a much deeper insight into technicalities and possibilities
• who develop or use a (shared-memory or distributed-memory) parallel software, and would like to boost the parallel efficiency of the code
• who need to debug a software (or a part of it) to optimize and improve its performance

Date

Tuesday 24 November and Wednesday 25 November, starting from 9:00 am until 17:00 pm.

Venue

Opleidingscentrum C KU Leuven Willem De Croylaan 52A BE-3001 Heverlee, Belgium

Prerequisites

• It is recommended to follow the basic training on 22-23 November: Registration via this link
• If you already have a VSC account, be ready to login to Tier-2 for the hands-on exercieses.